Performance Improvement of Ultra-Thin DRAM Package Using Fan-Out Wafer-Level Package

Ball grid array (BGA) package is the common package solution in memory products. With the demand for high-speed dynamic random access memory (DRAM) in AI training, wire bond cannot meet the electrical interconnect requirements of high-speed signals. To obtain less electrical resistance and loss during high-speed digital signal propagation, the DRAM is designed with advanced package technology, such as flip-chip (FC) and redistribution layer (RDL). Meanwhile, these technologies result in ultra-thin design, which also meet the requirement of reducing the thermal resistance and the length of signal routing to enhance the package's reliability and signal integrity. In the manufacturing opinion, the RDL-based Fan-out wafer level package (FOWLP), has the advantage of high production efficiency and the ability to achieve ultra-thin thickness, which is an efficient way to decrease the thickness of memory products and costs. Therefore, Fan-out process was applied to design a DRAM with thickness of 0.876mm, which was manufactured by using chip-first Fan-out process. Then, to verify the performance of the proposed Fan-out DRAM package, detailed comparisons among the window-BGA (wBGA), flip-chip chip-scale package (FCCSP), and Fan-out package are made, including the thermal simulation, electrical simulation, and warpage experiment test. Thermal simulation and measuring results show that the thermal and the warpage properties are better than wBGA and FCCSP. Furthermore, It is found that DRAM using the Fan-out package can reduce the parasitic parameter values.