Removal Method of Sidewall Scalloping in TSVs for Silicon Interposers and Applications of Smooth Vertical Cavities in Wafer-Level System Integration

When fabricating through-silicon-vias (TSVs) for interposers using a Bosch process to etch deep vias, scallops are usually generated on the sidewalls of the vias, which can lead to early device failure. In this paper, we present a practical method to reduce the sidewall scallops of deeply etched vias, employing a post-etching process with a low-concentration potassium hydroxide (KOH)-based solution. After etching in the KOH-based solution for 20 hours, the scallops on the sidewalls of the deeply etched vias became virtually unnoticeable, and the surface roughness was improved to less than 5 nm. The experimental results showed that the relatively low concentration of KOH, coupled with the addition of Isopropyl Alcohol (IPA) significantly reduced the sidewall scallops, while having negligible impact on the morphology of the vias. The process was carried out at room temperature instead of a high temperature annealing step, and was fully compatible with the backend of line (BEOL) processes. Besides, as an application of our sidewall scalloping removal method, vertical Fabry-Perot cavities were deeply etched on a silicon wafer and subsequently smoothed using the post-etching process. The clear observation of the Fabry-Perot interference spectrum was attributed to the smooth and vertical sidewalls, which significantly reduced light reflection losses. This measurement result indicated the potential for fabricating a variety of optical MEMS (Micro Electromechanical Systems) devices integrated in the silicon interposers using a combination of the Bosch process and post-etching technique.