Thermal Analysis and Optimization of Substrate Structural Parameters in High Power Density System-in-Package

This paper conducts thermal analysis and optimization for a specific high-power-density System-in-Package. By employing finite element analysis software ANSYS Icepak, the structure and parameters of the substrate were optimized to reduce the chip junction temperature of the System-in-Package, thereby enhancing the heat dissipation efficiency of the device. Firstly, single-factor analysis was conducted on the substrate structure and parameters affecting the heat dissipation of the packaging, including the number of vias, via plating thickness, copper layer thickness, copper coverage, substrate thickness, and BT material, to evaluate the influence of each factor on chip junction temperature and packaging thermal resistance. Next, the significance of the six parameters on chip junction temperature was analyzed through orthogonal experimental analysis. Finally, response surface analysis was conducted on the significant continuous variables to determine the optimal combination of substrate structure and parameters after optimization. The optimized chip junction temperature was 101.798°C, and the packaging thermal resistance was 27.43°C/W. Compared with before optimization, the chip junction temperature decreased by 15.23%, and the packaging thermal resistance decreased by 19.23%.