A Novel Intelligent Power Module in Embedded Packaging with Low Parasitic Inductance and Low Thermal Resistance

By combining embedding and 3D stacking techniques, a novel intelligent power module is introduced in this paper. The power stages are embedded and stacked in the organic substrates and the drivers are surface mounted on the board. The connection of gate drivers and power devices is conducted via copper wiring, leading to a shorter path and a smaller parasitic inductance. Specifically, the parasitic inductance of GS loop is decreased from 45 nH to 20 nH, reaching an almost 56% reduction. The SiC MOSFETs are stacked vertically to achieve half-bridge circuit and the inductance of DS loop is reduced from 5.4nH to 2.3 nH. Moreover, the power density is improved from 11.4 A/cm² to 18.2 A/cm². It is worth to mention that the heat sinks are directly bonded to the module by insulation material with high thermal conductivity, thus optimizing the heat dissipation path and improving the Rjf performance significantly.