Packaging Evaluations of SiC MOSFETs Based on Cu-Clip Interconnection Architecture

As SiC devices evolve towards higher power density, higher integration, higher voltage tolerance, higher switching frequency, and higher junction temperature tolerance, traditional Si-based packaging technologies can no longer meet the packaging requirements of SiC power devices. To further exploit the excellent characteristics of SiC MOSFETs, such as high thermal conductivity, wide bandgap, high switching speed, high operating temperature, and low on-resistance, it is imperative to explore new packaging processes suitable for current SiC devices. This paper employs the Clip interconnection architecture to replace traditional wire bonding, significantly enhancing the current-carrying capacity and heat dissipation capability of the circuits, while effectively reducing parasitic inductance. Compared to Al wire bonding, the Cu Clip interconnection architecture reduces the power loop resistance to 8.7% and the parasitic inductance to 57%. When a fixed power or current is applied to the power loop, the Cu Clip significantly improves the device's heat dissipation and current-carrying capabilities. Additionally, the effects of using Cu and Ag solders for Cu Clip sintering on SiC MOSFETs performance are compared, followed by an electro-thermal-magnetic performance evaluation of the SiC MOSFETs packaging process based on the Cu Clip interconnection architecture.