Optimization of Dual-Chip Heterogeneous Packaging Power Device Based on 3D Fan-Out Panel Level Packaging (3D FOPLP)

2.5D packaging and 3D packaging are both emerging semiconductor packaging technologies that can achieve high-speed and high-density interconnection between chips, thereby improving system performance and integration. The 2.5D packaging utilizes silicon interposer to achieve interconnection between chips, while 3D packaging directly designs through silicon via (TSV) in the chips to achieve stacked interconnection between multiple layers of chips. The current two packaging technologies are based on wafer level silicon intermediate layer and TSV process, mainly applied to IC chips such as logic chips and storage chips. Starting from the functions and application scenarios of the power devices, these two wafer level processes are actually not very suitable for power devices. Relatively speaking, FOPLP currently performs well on small area chips such as power devices, sensor chips, and RF chips, with advantages in conductivity, heat dissipation, and cost. In this study, based on the signal interconnection requirements between dual chips, a heterogeneous stacked packaging power device MOSFET & GaN was designed and manufactured. This 3D FOPLP design utilizes redistribution layers on the epoxy molding compound (EMC) dielectric layer and laser drilling between multiple layers of EMC to achieve vertical conduction between stacked chips and complete the electrical interconnection of the entire device. Compared to traditional wire bonding, the volume of this device based on 3D FOPLP technology has been reduced by about 60%, the static drain-source on-resistance (RDS(on)) was reduced by about 20%. The application of chip stacking integration to achieve the shortest interconnection and minimum packaging size in multi-chip power devices can achieve higher integration, better heat dissipation performance, and higher power transmission efficiency, thereby meeting the needs of multi-chip high-performance power devices.