Numerical Modeling and Experimental Study on Wafer Warpage of Embedded Interconnect Bridge in Organic Interposer

As artificial intelligence (AI) and high-performance computing (HPC) applications continue to grow in sophistication, the demand for data transfer is also increasing, which poses novel challenges to memory bandwidth and input/output (I/O) density. Faced with the limitations of traditional organic interposer in high density and multifunctionality, a localized ultra-fine interconnect multi-chip heterogeneous integration solution using embedded interconnect bridge in organic interposer is presented in this paper. However, the mismatch of coefficient of thermal expansion (CTE) between silicon-based bridge-chips and Ajinomoto Build-up Film (ABF) can cause wafer deformation under thermal stress, which is a critical issue that needs to be controlled effectively for successful subsequent processes of embedded interposer package. Aiming to analyze the problem of wafer warpage in embedded interposer package, a four-layer model is proposed with a bridge-chip embedded layer, a top build-up layer, a core layer that contains copper clad laminates (CCL), and a bottom build-up layer. Furthermore, the finite element analysis (FEA) is validated through Shadow Moiré experiment. The error between simulation and experimental results is less than 5%, which indicates that the four-layer model can predict wafer warpage behavior with high precision. In the warpage optimization analysis, the impact of structural parameters of embedded bridge-chips such as thickness, dimension, distance and height of copper pillars on wafer warpage is investigated based on the design of simulation approach and Taguchi method. It is found that the bridge-chip dimension is the critical factor controlling the wafer warpage behavior, and reducing it can significantly lessen the warpage.