Piezoelectric DC-DC Converters Benchmark in Power Management Integrated Circuit Context

In recent piezoelectric DC-DC converters (PRC) demonstrations, notable performance is achieved with discrete transistors and high input voltages (> 10's V). However, there's a gap in designs integrating all power switches on a single chip and targeting lower voltages. This study explores the influence of circuit technologies, switching frequency, and input voltage on PRC performance in the context of a fully integrated power stage. Unlike existing literature, our analysis factors in driving loss to define the frequency limit of the PRC. To achieve an optimal balance between efficiency and current density, we propose a systematic method for sizing the power stage and the piezoelectric resonator. Comparative results reveal that a power stage in classical CMOS technologies achieves efficiencies over 90% at frequencies in the 10's MHz range, including driving loss, at $\boldsymbol{0.3}\ \mathbf{A}/\mathbf{cm^{2}}$. Emerging GaN IC technologies demonstrate a 5x reduction in total power loss compared to Si-based counterparts. Lastly, a comparison of the three main PRC topologies unveils distinct design spaces, each offering unique advantages.