A Dual Loop Current Mode Feedback Capacitor Less LDO for High Current Applications

This paper presents a high speed, high current, capacitor less analog low dropout (LDO) voltage regulator using a dual loop architecture. The voltage feedback coupled with current feedback loop regulating the output is utilized in the proposed design. The voltage feedback provides accurate voltage regulation while the current feedback provides the feature of fast response to wide load changes. A feedforward line filter is employed to improve the power supply rejection ratio (PSRR) by making use of an extra path that directly affects the voltage at the gate of the power transistor. The proposed LDO is designed in a TSMC 180-nm 1.8 V standard CMOS technology. The overall design occupies an active area of 0.0131 mm² and can supply up to 500 mA at 1.2 V output while supporting load capacitance from 0 to 2 nF. During a 500 mA step-load, the transient response time is 3.1 µs with overshoot and undershoot of 132 mV and 156 mV, respectively. The measured PSRR is -43.78 dB at 10 kHz and -23.70 dB at 1 MHz when the line filter is activated.