Capacitively Isolated 400 Mbps Data Transfer System with 2 Ns Propagation Delay and 5 kV /µs Common Mode Transient Immunity

This paper presents the implementation and measurements of an isolated capacitively coupled data transfer system capable of sustaining a 355 Vrms breakdown voltage in a 3.3 V 0.18 µm CMOS process. The design is based on the pulse amplitude modulation scheme which consumes minimum silicon area and lower propagation delay. The receiver (Rx) demodulation circuit implements a pre-amplification stage to mitigate the common mode (CM) transient surge. Measurement results show that our fabricated chip prototype operates at a wide range of data rates between 1 kbps and 400 Mbps with a propagation delay of 2 ns. Moreover, the differential architecture achieves 5 kV/µs common mode transient immunity (CMTI). Our presented system shows a total energy consumption of 19.74 ×10³ pJ/b at 1 Mbps.