Optimization and Validation of Current Sharing in IGBT Modules With Multichips in Parallel

Multichips paralleled insulated gate bipolar transistor (IGBT) power modules are widely employed in industrial and automotive power conversion systems. The asymmetry of the circuit topology and the differences in chip characteristics are the main reasons for the unbalanced current distribution among parallel chips, leading to excessive electrical stress in power modules, which in turn forces the power modules to operate at a reduced rated current. Additionally, the unbalanced current distribution inevitably results in different chip losses, which are further amplified under high current loading conditions, causing some chips to be overheated, and significantly reducing the reliability. Optimizing the circuit topology is a common method to improve current distribution, but global changes often entail higher costs and longer development cycles. Moreover, the electrical parasitic of the fast recovery diodes (FRD) chip branches are not given sufficient attention in circuit topology research. Under rectification and blocked conditions in electric vehicles, FRDs often become the bottleneck for lifespan due to excessively high junction temperatures. Therefore, this article conducts a comparative analysis of the circuit parasitic in IGBT and FRD loops with several typical layouts, without changing the substrate and chip dimensions, and proposes a current sharing slot structure design to balance the parasitic parameters. Compared with the direct bonded copper (DBC) layout of the typical EconoDUAL power module, the optimized module reduces the current imbalance of FRD from 45.5% to 11.6% and the switching loss can be reduced by 8.6%. By adopting the current sharing groove, the parasitic parameter distribution can be further improved while maintaining a fixed DBC layout, considering the IGBT and FRD branches in concert. Finally, the steady-state and transient current sharing characteristics were verified under constant current and inverter conditions. Under constant current conditions, the temperature difference of FRD in the upper and lower parallel layout modules was reduced by 16.7 °C, and the junction temperature of IGBT was significantly lowered. Under inverter conditions, the highest junction temperature of the columnar layout modules could be reduced by 10 °C, and the temperature difference of FRD decreased by 62%. This article significantly optimizes the current imbalance issue through layout design, reduces the thermal equilibrium difference of the module under application conditions, and is conducive to improving the output capacity and fatigue life of the module, providing a solution for the design of power modules with high junction temperature operation capability and high-reliability.