An Efficient Dynamic Threshold Voltage Detection Scheme for Improving 3-D NAND Flash Reliability

With high storage density and large capacity, three-dimensional (3D) NAND flash utilizing multi-level storage technology has become the mainstream storage medium. Furthermore, by storing multiple bits in each flash cell, 3D NAND flash memory can achieve much larger storage capacity. However, the threshold voltage distribution in 3D NAND flash memory tends to shift after repeated program/erase and long retention time, leading to more detection error when adopting conventional fixed read reference voltage (RRV). To address this issue, in this work we investigate error characteristics of 3D floating-gate (FG) and charge-trap (CT) NAND flash memory, including the reliability variations of different layers and pages, and threshold voltage shifting. We propose an efficient dynamic threshold voltage detection (EDTVD) scheme by exploiting the error characteristics and the features of the data writing process of NAND flash to optimize RRV. Based on the Nanocycler test platform, the test results show that our proposed scheme can significantly reduce raw bit error rates (RBER) during reading processes and the step count is relatively low. The RBER of the EDTVD scheme is almost equal to the optimal read scheme, and the number of step count is close to 3 fixed-step read scheme.