Design of a Digital Control Fast Response Linear Regulator

A low-power and fast-response digital control low-dropout regulator (LDO) is designed in this study. The proposed architecture incorporates a cross-coupled transconductance unit for the current mirror, forming a current-mode transconductance error amplifier (CTA). The bias current of the CTA is digitally controlled, effectively adjusting the LDO’s transient response speed and static power consumption. Simultaneously, a voltage peak detection circuit and capacitively coupled branch are introduced to promptly sense changes in the output voltage, further enhancing the charging and discharging capabilities of the gate-source capacitance of the power transistor, thereby improving load transient response. Designed and simulated based on the TSMC 80nm CMOS process, the simulation results show that under digital signal control, during rapid load transitions $(100 \mu \mathrm{A} \sim 100 \mathrm{~mA} \text{@} 1 \mu \mathrm{s})$, in the strong control mode, the overshoot and undershoot voltages are 126 mV and 160 mV, with recovery times of $1.62 \mu \mathrm{s}$ and $1.51 \mu \mathrm{s}$, respectively. In the weak control mode, the overall static operating current of the circuit can be reduced to as low as $9.87 \mu \mathrm{A}$. Throughout the entire load range, the loop gain remains above 85 dB, exhibiting good phase margin, ensuring loop stability. Compared to traditional LDO circuits, this LDO circuit improves transient response speed, reduces static power consumption, and maintains a certain load-carrying capacity, thus offering favorable application conditions.