Advanced DFT Clock Control Architectures with Agile Development for Chisel-Based High Performance RISC-V Processors

The impact of clock distribution networks on the performance, power dissipation, and reliability of high-performance processors has been extensively studied. Designing a DFT clock control architecture that matches mainstream clock distribution networks while meeting the requirements of advanced DFT methodologies is crucial for improving the quality of DFT designs in high-performance processors. Building on the open-source high-performance RISC-V processor XiangShan, this paper presents cutting-edge DFT clock control architectures suitable for H-tree and clock mesh structures. It achieves true hierarchical testing and significantly optimizes DFT timing closure. Employing the agile development language Chisel, a versatile, parameterizable OCC that accommodates various clock networks was developed. In this paper, the use of Chisel as DFT EDA tool for developing the DFT clock control architecture provides a more agile and flexible DFT design flow, offering new insights for agile DFT design based on Chisel.