Ka-Band CMOS Variable-Gain Amplifier Using Capacitive Compensation Technique to Suppress Phase Error

In this study, we designed a Ka-band variable-gain amplifier (VGA) using a 65-nm RFCMOS process. A capacitive compensation technique was proposed to suppress the phase error of the CMOS VGA without the additional required chip area. To this end, the cascode structure widely used in CMOS VGAs was analyzed, and based on the analyzed results, a technique of using an additional capacitor in the drain node of the common-source transistor of the cascode structure was proposed to suppress phase error. Because the proposed technique may be implemented by adding only one shunt capacitor, it is possible to efficiently utilize the chip area. In order to verify the feasibility of the proposed capacitive compensation technique, an CMOS VGA was fabricated using a 65-nm RFCMOS process. In the operating frequency range of 26.5 GHz to 30.0 GHz, the variable gain range was measured to be 20.4 dB. In this case, the measured RMS phase error was suppressed to be lower than 1.0 . In addition, only one capacitor was added for the proposed technique, so the chip size was compactly designed to be 0.056 mm2.