Jitter-Based True Random Number Generator with Dynamic Selection Bit Reconfiguration

A compact, lightweight jitter-based True Random Number Generator (TRNG) is proposed in this paper. The key idea behind this design is to use a combination of high-entropy noise sources to select those same noise sources to operate at a time. This is achieved through cross-coupled connections and dynamic selection bit reconfiguration, reducing hardware consumption without compromising the quality of the generated bits. In cryptography and security, a TRNG plays a vital role in developing unique keys for encryption, thereby ensuring the integrity and protection of the system. The design utilizes various combinations of odd numbers of inverters to introduce jitter as a noise source to create Running Oscillators (RO). Moreover, the design employs multiplexers and a single XNOR logic gate for dynamic noise source selection. Finally, the area, speed, power, and energy of the proposed TRNG are measured using Synopsys Design Compiler (SDC) for 14nm, 32nm, and 45nm technology nodes. The randomness of this design is tested and validated using NIST SP800-22 tests. All 16 statistical tests for randomness outlined in the NIST test suite are passed without requiring post-processing circuitry. Hence, this TRNG design presents significant advancements in secure data risk management, offering an ultra-compact and efficient solution for generating secure keys.