A 3.04-fs FoM Hybrid LDO Regulator with Fast Transient Algorithm and Wide Load Range

This paper presents a novel approach to fast response low clock frequency hybrid LDO. The proposed design uses charge distribution to estimate the size of power transistor required to achieve the correct output voltage. This method significantly reduces the amount of clock cycles to achieve a steady state. In conjunction with the proposed digital algorithm, an analog error amplifier is added to the system to achieve zero current capability as well as improved voltage regulation at low load currents. In presence of the analog-assisted loop, an inverter based droop detector is implemented to reduce the undershoot and further increase conversion speed. The proposed LDO is design in a TSMC 180-nm 1.8 V standard CMOS process and analyzed using Spectre with BSIM3 device models. Post-layout simulation confirms that with a 10 MHz clock, the LDO is capable of providing up to 120 mA at a stable 1.2 V output. A 1.17 μs transient response for a full range load step with a maximum droop voltage of 253 mV is obtained.