A 3-MHz-3-GHz 8-Phase Reset-Free Anti-Harmonic Delay-Locked Loop Using Phase Difference Composition in 65-nm CMOS

This paper reports an 8-phase reset-free antiharmonic delay-locked loop (DLL). The proposed design overcomes the false and harmonic lock problems by applying the phase difference composition technique, which broadens the range of the phase detector to 141t. This range can be further expanded with more delay cells. The voltage-controlled delay cells are designed symmetrically to maintain the duty cycle, so there is no need to attach a duty cycle correction circuit to each clock output. This design does not need external reset or start signals, harmonic lock detectors, false lock detectors, auxiliary loops, replica delay lines, or multiple control voltages. The proposed DLL is implemented in 65-nm CMOS, and its operating frequency ranges from 3 MHz to 3 GHz. At 3 GHz, simulation results indicate a mean phase offset of 0.47 ps, and the DLL-contributed rms jitter is 0.328 ps.