Development of a Configurable Photon-to-Digital Converter in 65 nm

A photo-detector chain with a timing jitter below 10 ps will increase the resolution of high-energy physics experiments vertex reconstruction, quantum telecommunication and medical imaging. To achieve this, our team at Université de Sherbrooke is developing a Photon-to-Digital Converter (PDC), an array of single photon avalanche diodes (SPAD) coupled one-to-one by their cathodes to quenching circuits (QC). The prototype, designed in TSMC 65 nm LP technology, includes the full front-end chain required to detect and timestamp photons. The prototype time-to-digital converter (TDC) adopted in our design is a patented cascaded-stage Vernier TDC with reduced power consumption and area already validated in 180 nm technology. The circuit includes 2 arrays, one optimized for rad-hard applications, of $4 \times 4$ QCs connected to integrated CMOS 65 nm SPADs as the input and to TDCs at the output. The QC discriminator consists of an inverter chain capable of configuring its switching voltage to optimize the front-end’s timing jitter and reduce spurious counts due to the input noise. Furthermore, the QC follows the technology’s design for manufacturing rules to maximize the production yield. This work follows the design process and shows updates on PDC fabrication and preliminary results on the newly developed QC prototype.