An Area- and Power-Efficient 32-channel Multi-Energy Photon Counting Readout ASIC Using Successive Approximation Register Logic

In computed tomography (CT) X-ray imaging technology, the multi-energy window setting offers greater advantages in material decomposition and image quality. A traditional multi-energy discrimination photon counting circuit is typically implemented by a multiple-discriminator scheme, which employs multiple comparators to generate pulse signals and drives multiple counters for photon counting, within a single channel to implement the division of different energy windows. However, area overhead and static power consumption of each channel are significantly increased when the number of energy windows increases. This paper presents a novel circuit scheme based on peak detector voltage signals digitized by a successive approximation (SAR) analog-to-digital converter (ADC). The number of comparators will not increase with the extension of energy windows. A 32-channel front-end readout application-specific integrated circuit (ASIC) is designed in $0.35 \mu \mathrm{m}$ CMOS process with a die area of $4.8 \mathrm{~mm} \times 4.8 \mathrm{~mm}$. A charge-sensitive amplifier, a CR-RC pulse shaper, a gain amplifier, an event-driven peak detector and a 4-bit SAR ADC are integrated into each channel to discriminate and count incoming photon information through eight energy windows with a dynamic range of from 3 keV to 80 keV. The simulated equivalent noise charge is $53 \mathrm{e}^{-}$(rms) plus $4 \mathrm{e}^{-} / \mathrm{pF}$. The count rate is up to 1 Mcps under the power dissipation of about $4.9 \mathrm{~mW} /$ channel with a supply voltage of 3.3 V. The area overhead of the proposed circuit is shrunk by 5 times, and power consumption is reduced by 22%, compared with traditional multiple energy discrimination counting circuits.