A Low Power Multi-Bit Passive ΔΣ Modulator for Wearable Devices

We present a low-power multi-bit passive ΔΣ modulator for wearable devices. Though delta-sigma modulators (DSM) that use passive filters can achieve low-power operation, the lower gain of the filters in those modulators causes lower resolution. Some techniques that exploit the combination of passive and active filters and low-gain circuits have been proposed to improve the resolution, which causes significant power dissipation. In this study, we propose a modulator that is composed of a passive filter and a 2-bit Flash ADC with a low-power comparator to overcome the above issues. We implemented the proposed modulator in a 0.18 μm CMOS technology, which has a bandwidth of 10 kHz for a clock frequency of 1.28 MHz. The circuit simulation results show that the proposed circuit achieves a maximum SNDR of 54 dB and a dynamic range of 62 dB with 1.75 μW power dissipation.