A Sub-nanosecond Delay Floating-voltage Level Shifter for SiC MOSFETs Gate Driver Application

In order to meet the requirements for the design of SiC gate driver in terms of speed and dv/dt immunity, a sub-nanosecond delay level shifter based on a high-voltage (HV) digital level shifter circuit is proposed. It can decrease the response time compared with the existing level-shifting circuitry, enabling its application in high-voltage scenarios such as closed-loop drive circuits for silicon carbide. The edge detection circuit and simple pull-up branches are utilized to reduce the transmission delay and power consumption. The circuit is simulated at a frequency of 10MHz in a 018um BCD process with Virtuoso, and the results demonstrate that the average transmission delay is about 380ps and the charging response time of the slow path is reduced to 3.3ns.