Design of Adaptive Ramp Generator

VLSI testing is one of the most crucial parts of the IC manufacturing process. The complexity and cost involved in the testing phase is very high. Ramp signals play an important role in the built-in self-test of Analog to Digital Converters to ensure their (ADCs) proper operation. Ramps are used in place of sine waves in the ADC testing. The advantage of Ramp signal over sine wave is that the former is much more linear and simpler than the latter. One of the important metrics of ADC testing is the “offset error” which can be found from the output of ADC when the input is a Ramp signal but not when the input is a sine wave. Ramp signal generators available today are not fully linear. They have some non-linearities due to circuit parameters. This paper is presented with concepts covering the design of adaptive ramp generators with high- quality on-chip testing of Analog to Digital Converters. Existing basic ramp generators possess various problems in testing and lack of quality in accuracy. The proposed method of adaptive logic has better performance in terms of ramp linearity and slope precisions with low area over ahead. Using the ramp signal from the proposed method will improve the accuracy of ADC testing (Built-In Self-Test).