A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections

Routing is the most time-consuming step in the implementation flow of FPGA designs. With the advance in transistor scaling and system integration, hardware resources in FPGA devices are growing in a larger quantity and diversity. The routing architecture is designed to be more complicated for mapping RTL designs to FPGA devices correctly, which brings significant challenges for current FPGA routing algorithms. The key challenges for routing algorithms lie in large solution space and heavy congestion, especially for high-fanout nets. We propose a partition-based algorithm to accelerate the routing of high-fanout nets, which decomposes the global routing guide to shrink the search space for connecting each sink. Meanwhile, the congestions existing inside CLB are hard to handle by traditional sequential negotiation-based algorithms, because the industrial routing architecture is quite complex. We propose a concurrent intra-CLB rerouting algorithm to effectively resolve routing congestion inside a CLB tile induced by connections between intra-CLB logic pins, e.g., logic elements and switch boxes. Experimental results on modified ISPD2016 benchmarks demonstrate that our framework can achieve 100% routability in 9.8% less wirelength and 11× less runtime, while the state-of-the-art VTR 8.0 routing algorithm fails at 7 of 12 benchmarks.