Reconfigurable Radar Signal Processing Accelerator for Integrated Sensing and Communication System

IEEE 802.11ad-based integrated sensing and communications (ISAC) have been identified as a potential solution for enabling next-generation intelligent transportation systems in the millimeter wave (mmW) spectrum. The radar functionality within the ISAC enables accurate detection and localization of mobile targets, which can significantly speed up the selection of the optimal high-directional narrow beam required for mmW communications between the base station (BS) and mobile target. To bring ISAC to reality, a radar signal processing (RSP) accelerator, colocated with the wireless communication physical layer (PHY), on edge platforms, is desired. In this work, we discuss the 3-D digital hardware RSP framework for 802.11ad-based ISAC to detect the range, azimuth, and Doppler velocity of multiple targets. We present an efficient reconfigurable architecture for RSP on multiprocessor system-on-chip via hardware-software codesign, word-length optimization, and serial-parallel configurations. We demonstrate the functional correctness of the proposed fixed-point architecture and significant savings in resource utilization ($\sim 40\%\hbox{--}70\%$), execution time ($1.5 \times$ improvement), and power consumption (50%) over floating-point architecture. The acceleration on hardware offers a 120-factor improvement in execution time over the benchmark quad-core processor. The proposed architecture enables on-the-fly reconfigurability to support different azimuth precision and Doppler velocity resolution, offering a real-time tradeoff between functional accuracy and detection time. We implement end-to-end ISAC comprising RSP and PHY on MPSoC and demonstrate significant improvement in throughput over IEEE 802.11ad.