3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications

Row decoder leakage saving (RDLS) and high-speed write driver leakage saving (HS-WDLS) circuits are proposed to reduce leakage power while keeping high access speed. The proposed circuits achieve a 71% reduction in leakage power. Additionally, a detailed discussion on the trade-off between switching current increase and leakage current reduction is presented. The overhead of switching power is 0.3% and 1.9% for read and write operations, respectively. Simulation results show that our static random-access memory (SRAM) has actual power reduction when active rate is lower than 21% at $25~^{\circ }$ C, 81% at $75~^{\circ }$ C, and 100% at $85~^{\circ }$ C or higher. Silicon measurements demonstrate that it operates at a frequency of 3.7 GHz at 1.4 V and has a wide-range operation down to 0.5 V. It achieves the best figure of merit (FoM), defined as density $\times F_{\max }$ .