Modeling and Design Guideline of Optimal Split Inductance Range for Split-Output Power Module Considering Normal and Fault Conditions

Split-output structure outperforms the common halfbridge structure for silicon carbide (SiC) applications in terms of operation efficiency increasing, crosstalk voltage suppression, and zero dead time. An appropriate split inductance is the key to fully exploiting the potentials of the split-output structure. However, the split inductance design is empirical and lacks a theoretical guideline. Therefore, in this paper, models in the s-domain are established to quantitatively illustrate the effects of the split inductance on the characteristics of normal operation and shortcircuit faults, respectively. The accuracy of the models is verified by experiments. The lower limit of the split inductance is determined to obtain the lowest switching loss and safe crosstalk voltage. It is also observed that the upper limit also exists to avoid undesirable oscillation and excessive short-circuit thermal stress. As a result, a general design guideline is presented to determine the optimal split inductance range, relying only on the application conditions and datasheet parameters