Gate Switching Lifetime of P-Gate GaN HEMT: Circuit Characterization and Generalized Model

In converter operations, a major reliability concern of the GaN HEMT with a p-GaN gate (i.e., p-gate GaN HEMT) is the very small gate overvoltage margin. Despite many reliability studies using DC bias and pulse I-V test, the gate reliability under the application-use condition has been seldom reported for p-gate GaN HEMTs. Meanwhile, due to the unique electrostatics of the p-GaN gate, the applicability of the conventional DC lifetime model to p-gate GaN HEMTs is questionable. To address these gaps, this work develops a new circuit method to produce the application-like gate voltage (VG) stress that consists of a resonant ringing added to an operational DC bias. Using this circuit method, the gate lifetime of commercial p-gate GaN HEMTs is characterized under multiple variables, including the DC bias, peak ringing VG (VG(PK)), ringing pulse width (PW), switching frequency (fSW), and temperature (T). The lifetime is found to show complex relations with the VG(PK), PW and fSW, as well as a positive temperature dependence. Based on the statistical data, a gate switching lifetime model is constructed for the first time for p-gate GaN HEMTs. This model comprises the VG-, fSW-, T-related Acceleration Functions and allows one to determine overvoltage stress from an arbitrary VG waveform and further calculate the gate lifetime. The gate reliability is revealed to be an increasingly significant concern under high fSW, low T, and increased parasitics in the driver loop. The new characterization circuit and switching lifetime model underscore the importance of application-based reliability methodology. The characterization results suggest the need for performing gate qualification for p-gate GaN HEMTs under high-fSW, low-T switching conditions