Reliability Improvement of 2-D WSe₂ FETs by Regulating Charge Trapping: An Ab Initio Demonstration

2-D field-effect transistors (FETs) hold great promise for achieving further integrated electronics and extending the life of Moore’s law. However, amorphous SiO₂ (a-SiO₂) with a high density of defects always results in significant charge trapping issues and further inhibits the realization of high-performance and high-reliability 2-D FETs. Here, taking WSe₂ FETs as an example, we investigate the charge trapping phenomenon and the accompanied threshold voltage shift issue in 2-D FETs, and endeavor to figure out ways to suppress them. First, by combining ab initio calculations with experiments, an unequal electron/hole trapping capability and an asymmetric hysteresis loop are predicted and confirmed. Second, through the atomic level to device level simulations, we demonstrate the effectiveness of spacing layers such as hexagonal boron nitride (hBN) and vacuum in improving device reliability. Interestingly, it is found that the vacuum is more effective under small gate voltage, while the hBN layers are more excellent under large gate voltage. These findings present a clear picture of charge trapping in WSe₂ FETs and provide explicit guidance to improve their reliability.