A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk

Time-interleaved (TI) analog-to-digital converters (ADCs) are an established architecture, but fundamental problems still exist that prevent replicating the performance of each sub-ADC to the overall TI ADC. This article presents different techniques to overcome the main challenges in implementing an interleaved converter: 1) driving the ADC with sufficient linearity and bandwidth; 2) avoiding the crosstalk through the reference voltage; and 3) mitigating the effect of inter-channel mismatches. The proposed techniques are applied to a 2-GS/s TI ADC implemented in a TSMC 28-nm bulk CMOS process consisting of eight 11-bit 250-MS/s successive approximation register (SAR) ADCs. The prototype achieves a signal-to-noise plus distortion ratio (SNDR) and a spurious-free dynamic range (SFDR) of 57.3 dB and $\mathrm {70.1~dBc }$ , respectively. The SNDR degrades on average by only 1.76 dB compared with the sub-ADCs, demonstrating the effectiveness of the proposed techniques. With a power consumption of 118.6 mW, including input buffer, digital calibrations, and SAR ADCs, the TI ADC achieves a $\mathrm {99~\text {d}\text {J} /\mathrm {conv-step} }$ Walden figure of merit (FoM) and a 156.6 dB Schreier FoM.