Extremely Scaled Perpendicular SOT-MRAM Array Integration on 300mm Wafer

We present a novel integration solution to prevent MTJ pillar damage due to patterning of SOT- MRAM devices, particularly when targeting the ultimate SOT track scaling. Substantial reduction of switching current with pulse widths down to 0.3ns is shown in single cell extremely scaled devices versus our baseline. We demonstrate, for the first time, the functionality of a perpendicular SOT-MRAM array on 300mm CMOS wafer, comprising of multiple 4kb sub-banks with variations in SOT track size and pitch at our baseline 63nm MTJ CD. Study of the 4kb sub-banks indicates the feasibility of device pitch scaling from a device-to-device gap of 216nm down to 99nm, leading to a 50% increase in the MTJ read window (median Rp to Rap) while obtaining remarkable tailing bits as low as 0.3% for W/CoFeB stack (Wß SOT track with CoFeB free layer MTJ). Finally, we validate the scalability of the SOT devices on a BEOL compatible 400°C Pt/HFL stack (Pt-based track with a hybrid free layer system), highlighting the practical applicability and versatility of our approach.