Design of High-Performance while Energy-Efficient Microprocessor with Novel Asynchronous Techniques: (PhD Forum Paper)

Design of high-performance processors with low power is the primary goal of many contemporary and futuristic applications, while asynchronous circuit is one of the solution. This brief presents a novel RISC-V microprocessor architecture which is capable of achieving these requirements by using two proposed asynchronous techniques. The first contribution is a relative-timing based asynchronous controller (RTAC), which is very small (only 7 gates) and low-power when compared to other existing controllers. The second contribution is a novel quasi-2phase handshake protocol which combines the benefits of the traditional 2-phase and 4-phase protocols, it allows a simple 4-phase asynchronous controller to achieve the same throughput as a 2-phase circuit. The simulation results proved that an asynchronous multiplier adopted the quasi-2phase protocol has approximately 1.95 times throughput higher than the 4-phase one. Finally, the key technologies of this work will be thoroughly validated in a 3-stage 32bits RISC-V microprocessor to further demonstrate the feasibility of the proposed techniques.