Towards Zero-Trust Hardware Architectures in Safety and Security Critical System-on-Chips

Edge computing applications have strict requirements for latency, throughput, and energy. Increasingly, there are more safety and security requirements due to system-level threats that have been discovered in current SoCs. To address these issues, the research community proposed multiple novel solutions aimed at patching the uncovered threats. Nowadays, open hardware SoC platforms have reached an impressive level of maturity. We believe that such a level of maturity provides interesting opportunities for the research community for the integration, development, and evaluation of innovative methodologies for enhancing the security and safety of next-generation SoCs. In this paper, we describe some of these opportunities we believe are relevant, including system-level architectural extensions, fine-grained timing analysis, and novel methodologies for security and safety verification. Combined, these methodologies can ease the certification process in critical systems and eventually contribute to enhancing security and safety in the next generation of commercial SoCs for critical-edge applications.