Efficient Design of a Double Tail Dynamic Comparator for High Speed and Low Power Applications in 90nm Technology

The double tail dynamic comparator (DTDC) described in this study has fast speed but little power. The conventional single tail comparator designs have a faster response time but has a high power dissipation and kickback noise. In the proposal architecture, 2 PMOS switch transistors, MR4 and MR5, have been included to the latch stage to allow a regenerating latch that consumes less power and activates faster with a reduced kickback noise. The 90 nm CMOS technology is used for the design and simulations, with a 0.8 V supply voltage and a 1 GHz clock frequency. The simulation results verify that the suggested DTDC has much lower power consumption. The consumption of power is 327 nW, the delay and slew rate are 240 ps and 3.33 V/ns.