A Novel Dielectric Modulated Double Gate Charge-Trapping MOSFET: Ferroelectric Gate Stack and Gaussian Doped Substrate Integration for Enhanced Performance

His paper investigates the operational characteristics and performance metrics of a novel double gate charge-trapping metal oxide semiconductor field effect transistor (DG-MOSFET) that incorporates a ferroelectric gate stack, a Gaussian-doped multilayered substrate, and a buried oxide layer. The study utilizes Silvaco TCAD(Technology Computer-Aided Design) Atlas for device simulation and analysis. A comprehensive comparison between the proposed DG-MOSFET, a conventional DG-MOSFET, and other variations, has been presented. Through detailed simulations and analysis, the paper evaluates key parameters including threshold voltage, subthreshold swing, drain-induced barrier lowering (DIBL), on/off current ratio, and transconductance. Different modifications were carried out and their implications were compared to study device performance. Results indicate that the proposed DG-MOSFET exhibits superior performance characteristics compared to both reference devices, showcasing enhanced carrier mobility, reduced leakage current, and improved subthreshold behavior. Furthermore, the Gaussian doped multilayered substrate contributes to mitigating short-channel effects, enhancing overall device scalability and reliability. his paper investigates the operational characteristics and performance metrics of a novel double gate charge-trapping metal oxide semiconductor field effect transistor (DG-MOSFET) that incorporates a ferroelectric gate stack, a Gaussian-doped multilayered substrate, and a buried oxide layer. The study utilizes Silvaco TCAD(Technology Computer-Aided Design) Atlas for device simulation and analysis. A comprehensive comparison between the proposed DG-MOSFET, a conventional DG-MOSFET, and other variations, has been presented. Through detailed simulations and analysis, the paper evaluates key parameters including threshold voltage, subthreshold swing, drain-induced barrier lowering (DIBL), on/off current ratio, and transconductance. Different modifications were carried out and their implications were compared to study device performance. Results indicate that the proposed DG-MOSFET exhibits superior performance characteristics compared to both reference devices, showcasing enhanced carrier mobility, reduced leakage current, and improved subthreshold behavior. Furthermore, the Gaussian doped multilayered substrate contributes to mitigating short-channel effects, enhancing overall device scalability and reliability. T