A 12-nm High-Density Energy-Efficient 1-Mb 2R2W Scratchpad With Local Blocks for Neural Network Applications

With the increasing scale and complexity of neural networks, high-bandwidth multi-port scratchpads become critical to improve system performance and energy efficiency. However, conventional multi-port scratchpad features a low storage density and a small memory capacity, resulting in limited performance improvements. In this article, we propose a high-density and energy-efficient scratchpad with two read and two write (2R2W) ports based on customized local blocks and a hierarchical accessing approach. Specifically, different global ports can access different blocks at the same time, where local read or write operations are performed with single-port bitcells. For an optimal storage density, push-rule high-density bitcells are used with metal pitch-matched local peripheries inside the block. Besides, hierarchical wordline decoding and fishbone-like vertical signal routing are presented to mitigate the density loss due to massive global signals. To improve the energy efficiency, dual-swing signaling, hierarchical timing scheme, and cascade sensing scheme are developed with negligible area overhead. A 1-Mb 2R2W scratchpad is prototyped in a 12-nm FinFET CMOS technology, achieving a storage density of 3.73 bit/ $\mu $ m2, which is superior to the state-of-the-art (SotA). The measurements demonstrate functionality from 180 MHz at 0.45 V to 950 MHz at 0.8 V, and a peak energy efficiency of 44.1 Tbps/W, which is 72.3% higher than SotA. Thus, with area-aware design strategies and energy-efficient circuit techniques, the proposed multi-port scratchpad is beneficial for neural network applications.