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A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference | IEEE Journals & Magazine | IEEE Xplore

A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference


Abstract:

Compute-in-memory (CIM) is promising in reducing data movement energy and providing large bandwidth for matrix-vector multiplies (MVMs). However, existing work still face...Show More

Abstract:

Compute-in-memory (CIM) is promising in reducing data movement energy and providing large bandwidth for matrix-vector multiplies (MVMs). However, existing work still faces various challenges, such as the digital logic overhead caused by the multiply-add operations (OPs) and structural sparsity. This article presents a 2-to-8-b scalable approximate digital SRAM-based CIM macro co-designed with a multiply-less neural network (NN) approach. It incorporates dynamic-logic-based approximate circuits for the logic area and energy saving by eliminating multiplications. A prototype is fabricated in 28-nm CMOS technology and achieves peak multiply-accumulate (MAC)-level energy efficiency of 102 TOPS/W for 8-b operations. The NN model deployment flow is used to demonstrate CIFAR-10 and ImageNet classification with ResNet-20 and ResNet-50 style multiply-less models, respectively, achieving the accuracy of 91.74% and 74.8% with 8-bit weights and activations.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 60, Issue: 2, February 2025)
Page(s): 695 - 706
Date of Publication: 05 August 2024

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