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Experimental Demonstration of Field-Free STT-Assisted SOT-MRAM (SAS-MRAM) With Four Bits per SOT Programming Line | IEEE Journals & Magazine | IEEE Xplore

Experimental Demonstration of Field-Free STT-Assisted SOT-MRAM (SAS-MRAM) With Four Bits per SOT Programming Line


Abstract:

SAS-MRAM has been proposed as a potential last-level cache SRAM replacement owing to its high speed (~1 ns), high cell density, and high endurance characteristics. Here, ...Show More

Abstract:

SAS-MRAM has been proposed as a potential last-level cache SRAM replacement owing to its high speed (~1 ns), high cell density, and high endurance characteristics. Here, we report a first-of-its-kind experimental demonstration of simultaneous switching of 4 magnetic tunnel junctions (MTJs) with different polarity on the same spin-orbit torque (SOT) write line. We experimentally verify the novel SAS-MRAM writing scheme which overcomes the unique disturb modes found in the shared SOT line structure and enables simultaneous, field-free switching of multiple MTJs. The non-volatility of SAS-MRAM promises advantages in energy efficient computing applications such as edge AI over SRAM.
Published in: IEEE Electron Device Letters ( Volume: 45, Issue: 10, October 2024)
Page(s): 1800 - 1803
Date of Publication: 02 August 2024

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