A Test, Debug, and Silicon Lifecycle Management Architecture for a UCIe-Based Open Chiplet Ecosystem

In the last few years, chiplets have become foundational to continuing the pace of innovation. The chiplet market is projected to significantly ramp up in the next few years, and we need to be able to support chiplets from multiple vendors in the same package. These realities create new test and debug challenges through all stages of chiplet productization from sort to in field. There is a scaling challenge to test and debug efficiently without growing package pin count; there is a challenge of test time reduction and interoperability when testing and debugging with chiplets from multiple vendors. Additionally, silicon lifecycle management (SLM) of chiplets in a system in package (SIP) for manufacturing quality monitoring and in-field predictive analysis is a significant challenge. This article presents a comprehensive test, debug, and SLM architecture for addressing these challenges in a Universal Chiplet Interconnect Express-based SIP, paving the way for an open chiplet ecosystem.