130+ ps Coincident Time Resolution With 20-mm Crystal Length Using 28-nm Xilinx FPGA

The coincidence time resolution (CTR) is of paramount importance in positron emission tomography (PET) as it can directly determine the imaging resolution. In this article, a 130+ ps CTR with 20-mm crystal length is achieved using AMD FPGA platform. Three steps are proposed to achieve a high CTR. First, a low-noise amplifier (LNA) is used on fast output signals that are used for time sampling. This can equivalently lower the configured threshold for leading edge discriminator and therefore further mitigate the time walk effect. Second, a new time-to-digital converter (TDC) architecture that achieves less than 1-LSB integral nonlinearity (INL) and differential nonlinearity (DNL) without any calibration tricks are introduced. This TDC can yield salient INL performance, which can deliver consistent performance in time sampling and hence better CTR. Last but not least, a resource-efficient energy characterization method is proposed. This approach utilizes only one TDC chain to sample all trigger times for pulse reconstruction. This not only saves up to 75% chain resources but also minimizes sampling errors due to heterogeneity properties when involving multiple TDC chains. A prototype using 28-nm Kintex 7 FPGA is implemented and 130+ ps CTR is achieved.