Design and Implementation of the MTP Compiler

In the semiconductor storage domain, the swift advancement of Static Random-Access Memory (SRAM) has been significantly accelerated by the extensive adoption of sophisticated SRAM Compiler tools. These instruments enable the rapid generation of tailor-made SRAM memory arrays, effectively addressing specific design requirements. Nonetheless, the development of comparable compiler technologies for other types of memory, such as Multiple-Time Programmable (MTP) memory, has been notably absent. Our study fills this void by introducing a groundbreaking MTP Compiler that is both parameter-driven and compatible across different processes. Leveraging the capabilities of the TED electronic design automation tool, this innovative compiler facilitates the expedited production of MTP circuits and layouts for a broad spectrum of capacities, catering to diverse design needs. Its adaptable architecture is especially proficient at accommodating changes in process nodes, significantly reducing the time and effort required for the development of MTP memory technologies. This advancement streamlining the path from concept to production for MTP memories.