Comparative Analysis of the Characteristics of Clock Network Structures Buffer Tree, H-tree, Clock Mesh for Technological Nodes 28nm and 90nm

As technology advances, traditional clock network design methods are becoming less effective for creating competitive, high-performance, and energy-efficient complex circuits. It is especially important to improve the efficiency of clock networks in conditions of limited choice of technological processes. One way to increase the efficiency of a clock network is to use different topological structures and their hybrid variants. To develop the given topic, it was decided to investigate the following question: are there any prospects for using different topological structures in order to increase performance and reduce energy consumption? The article presents the results of a comparative analysis and modeling of topological structures Buffer tree, H-tree, Clock mesh on technological processes of 28 nm and 90 nm. A special feature of this work is modeling with different filling densities of library elements on the crystal area at the PrePlace stage ($\mathbf{3 0 \%}, \mathbf{5 0 \%}$, $70 \%$), as well as with different square shapes of the same dimension for H-tree and Clock mesh structures. Chapter 1 provides an introduction to the subject of the study, statement of purpose and novelty. Chapter 2 talks about the clock network and what time and power parameters are used in the analysis. Chapter 3 describes the topological structures: Buffer tree, Htree, Clock mesh. Chapter 4 describes the test environment and restrictions that were used in the analysis. Chapters 5-7 analyze designs using 90 nm and 28 nm process technology. Chapters 8 and 9 discuss the results and conclusions.