A 66 $\mu \mathrm{W}$ Asynchronous Time-Domain Bulk-Tuned Offset Cancellation Circuit for High-Precision Dynamic Comparator

This paper proposes a novel asynchronous high-precision, low-power, time-domain bulk-tuned offset cancellation technique for high-speed dynamic comparator. The proposed offset cancellation technique minimizes the offset by using bulk-tuning in conjunction with offset sampling in the time domain. The proposed phase detector eliminates the dead zone and is symmetric to both outputs. An energy and area-efficient charge pump with offset polarity-based selectivity is also introduced. The proposed offset cancellation scheme is implemented in 65-nm CMOS technology with a 1.2 V supply, and analytical modeling of the time difference of comparator outputs and offset is also presented. The proposed design has a power consumption of 65.8
$\mu \mathrm{W}$
and maintains a calibration speed of 1 GHz with the comparator operating at 2 GHz frequency. The standard deviation of the offset is decreased to 33.3
$\mu \mathrm{V}$
from 2.183 mV, qualifying it for high-speed, high-precision applications.