Process test chip for Josephson integrated circuits

Process test chips are fabricated along with chips containing experimental circuits in our laboratory in order to aid in forming a data base to characterize the technology. All the test sites are placed on a 6.35mm × 6.35mm chip with two distinct final wiring patterns. Wafers containing two chips of both types are processed along with the other substrates. Testing is done at the end of the run. Sites containing repetitive elements are populated at 1-10% of LSI density.