2µm - bubble device optimization

We report on the improvement in 8-9μm period devices as compared to simple scaling of the present state-of-the-art 16μm period devices. Optimizations of garnet, and processing parameters and device component design were made to reduce the chip drive (field, voltage). We found that the using larger bubble size than the scaled down value (2.2μm instead of 1.7μm) is most effective in reducing the drive field and improving gap tolerance. Conductor and permalloy thickness were kept at 3500Å (scaled down value is ≈2000Å). The spacer thickness, however, was close to the scaled down value of 4000 to 4500Å to improve the stretcher upper bias margin. Although non-planar devices sometimes showed very good margins at low drive fields (10% at 50 Oe drive), it is felt that planar processing is necessary to maintain reproducibility. Device component design based on extra large permalloy element such as double period major loops and 3π-corner in the replicator switch were found to have good overall bias margins of 26 Oe at 45 to 55 Oe drives. Operation at 150 kHz with 55 Oe drive showed as bias margin of 10% or more in the temperature range of -25 to 80°C. At 250 kHz an increase of 5 Oe in the minimum drive field was observed.