A Noise and Mismatch Improved Charge Pump for PLL in 28nm CMOS Technology

Conventional H-bridge charge pump (Hcp) is a well-known architecture for type-2 Phase-Locked-Loop (PLL) applications. However, this has significant noise and mismatch due to random variation of CMOS devices. Replica-assisted HCP will improve the mismatch due to VDS mismatch, but it can't improve the random mismatch. In this paper, a resistor-based Charge Pump (CP), which produces the CP current by using a voltage-to-current converter (V to I converter), has been proposed. This will improve the mismatch sensitivity and thermal noise due to the inherent mismatch performance of the resistor. The proposed resistor-based CP has been designed to produce $120\upmu\ \mathrm{A}$ current for a 1 MHz Bandwidth type-II PLL application in 28 nm CMOS technology. The postsimulation results show 0.8 % mismatch (sigma) and $115\ \text{dBc}/\text{Hz}$ thermal noise at 1 MHz frequency. The mismatch performance is 1.89x better than the existing one while checking on 200 Monte Carlo (MC) simulations. This consumes $120\upmu\ \mathrm{W}$ power from a 1 V nominal supply and occupies an area of $15200\ \upmu^{2}$ silicon area, including decoupling capacitors.