Investigation and Implementation of AI-HDLCoder for Automated VHDL Code Synthesis and Code Generation for Hardware SoC Development

The field of FPGA technology has recently gained significant attention as it enables complex hardware and software building blocks to be integrated onto a single reconfigurable platform. This commonly involves employing hardware description languages like VHDL and Verilog for effectively combining basic logic gates and describing digital and mixed-signal systems in either a concurrent or sequential manner. Due to the specialized nature of this domain and its alignment with wider programming audiences, hardware developers have also created tools such as MyHDL, SpinalHDL, SystemC. These aim to streamline development time and facilitate hardware concurrency modelling using popular languages such as C, Python and Scala. Practical experience has shown that an usage of high-level programming languages in backend provides some benefits, however an accurate code conversion and minimizing of development time struggles with coder's unstandardized syntax specifications, ongoing ecosystem support, and collaborative problem-solving by an involved wide community. This paper presents and showcases the AI-HDLCoder, an approach for VHDL synthesis and code generation within a SoC development process. It evaluates applying transformer-based natural language models to enhance and streamline the automation of producing VHDL code directly from design requirements, without reliance on additional intermediate parsing steps common among other existing options. The work also shows synthesized code examples of AI-HDLCoder and its comparison with MyHDL, emphasizing the accuracy that coder offers for future implementation background of numerous FPGA designs.