Design and Evaluation of Low Power 2 to 4 Decoder Circuit Using Three and Four Transistors NAND Gates

This paper presents a new design of a 2 to 4 decoder constructed using 3-transistor NAND gates, contrasting it with the conventional 4 transistor NAND gate-based technique. The primary aim of this paper is to exhibit advancements in power efficiency, worst-case propagation time delay, and power delay product (PDP). These improvements underscore the efficacy of the 3-transistor NAND gate-based design, illustrating its potential for efficient and optimized decoder architectures. The simulation of the design is carried out using SPICE with 250nm technology.