Inductance measurements of superconducting chip-to-package connectors suitable for Josephson LSI technology

It is necessary in any interconnection scheme used in LSI to be able to pass high-speed pulses from chip-to-chip through the package with a minimum of distortion while at the same time maximizing the number of input/output connectors (I/O's) in large arrays of densely packed connectors. We have measured the inductances (both self and mutual) of chip-to-package connectors which were arranged in a peripheral row around the edge of the circuit chip. The largest self-inductance measured for an 8:1 ratio of I/O's to ground connectors is low enough so that signals with a 30 ps time constant propagate through the connector without significant distortion. The largest self-inductance ranges from 28 pH for the linear array of eight connectors between grounds to 19 pH for four connectors between grounds. These results indicate that the electrical properties of these connectors are satisfactory for the LSI technology application of Josephson devices.