Synchronous, Low-Latency, Off-Module Interface for the IBM z16 Telum Processor

This article describes the IBM z16 off-module high-speed serializer/deserializer interface that connects Telum Processor chips. The crosspoint interface bus (X-bus) is designed to provide low-latency data transfer via a synchronous design for scalable system performance while supporting a dynamic, asynchronous mode to handle clocking failures and lane degrades. High availability is achieved through data packet protection, command voting, cancel, data replay recovery, interface retraining, and lane degrade. The z16 X-bus design is described in the context of two alternatives: a wide, parallel, synchronous, low-latency interface with error correction and a narrow, serial, asynchronous, high-latency interface with error detection and replay, both of which fall short of the high performance and low pin count required for the reliable, tightly coupled, coherent, symmetrical multiprocessor system.